Jobs / United States / Astera Labs INC
Principal Emulation Engineer
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles3 certified filings for “Emulation Engineer” (Computer Hardware Engineers) in CA: $150k–$230k, median $230k. Most were filed at wage level IV (67%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Emulation Engineer — San Jose, CA Role Overview As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone. Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role, you’ll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales. Key Responsibilities • Emulation and Prototyping • Architect, build, and maintain emulation environments for complex ASICs and SoCs. • Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation. • Enable verification teams to stress-test designs with scalable, repeatable emulation workflows. • Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation. • Protocol and SoC Verification • Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams. • Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe , SPI, I2C/I3C, and similar interfaces. • Analyze protocol behavior, functional coverage, performance, and corner cases across complex server , storage, and networking systems. • Translate system requirements into practical emulation scenarios, tests, checkers, and measurable verification goals. • Debug and Technical Leadership • Debug design, environment, transactor, software, and test-code issues across the emulation stack. • Identify software and hardware co-simulation limitations and apply effective isolation and debug techniques. • Partner with cross-functional teams to prioritize a dynamic workload, resolve issues quickly, and drive risks to closure. • Provide technical leadership, communicate clearly, and operate effectively with minimal guidance and supervision. Basic Qualifications • Bachelor’s degree in Electrical Engineering , Computer Engineering, Computer Science, or a related technical field. • 8–12 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications. • Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs. • Working knowledge of PCI Express Gen 3 or later, CXL, UALink , Ethernet, DDR, NVMe , SPI, I2C/I3C, or similar communication protocols. • High proficiency in SystemVerilog