Jobs / United States / Astera Labs INC
Principal Physical Design Engineer
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is redefining the connectivity fabric that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world's largest AI clusters — driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market. This is a hands-on technical leadership role. You will architect physical design methodology, mentor senior engineers, and partner closely with RTL, DFT, analog, and package teams to take our next generation of connectivity silicon from RTL to tapeout on leading-edge nodes. Key Responsibilities • End-to-End RTL2GDS Ownership • Own the full RTL2GDS flow on advanced process nodes — synthesis, floorplan, placement, CTS, routing, and signoff — across Astera's connectivity product portfolio • Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs • Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets • Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab • Timing, Power & Signoff • Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff • Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure • Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around • Technical Leadership & Cross-Functional Partnership • Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies • Establish and evolve physical design methodology, scripts, and flows across the team • Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field • 8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below) • Deep expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime) • Strong command of low-power design techniques (multi-Vt, power gating, DVFS, UPF) • Proficiency in Tcl/Python scripting for flow automation • Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production Preferred Qualifications • MS in Electrical Engineering or Computer Engineering • Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs • Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates) • Familiarity with EMIR, thermal, and package co-design considerations • Experience mentoring senior engineers and driving methodolo