Jobs / United States / Astera Labs INC
Principal Physical Design Engineer -EMIR & Power Integrity
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Principal Physical Design Engineer , you will own IR drop and electromigration (EMIR) analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout. You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery, meet foundry sign-off criteria, and prevent long-term reliability issues in production silicon. This role is fully on-site at our San Jose, CA location. Key Responsibilities • Power Integrity Analysis & Sign-off • Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, driving closure to foundry sign-off criteria • Drive UPF-based power domain planning and power-aware sign-off across multi-voltage designs • Analyze thermal and current density issues and recommend design modifications to ensure long-term reliability • Design Convergence & Cross-Functional Partnership • Collaborate with package, power grid, and floorplan teams to identify and resolve voltage drop hotspots and EM violations early in the design cycle • Provide actionable feedback to implementation teams on power grid reinforcement, decap strategy, and hard-macro / SerDes integration • Partner with RTL, STA, verification, IP vendors, and foundry to drive power integrity convergence through tapeout • Methodology & Automation • Develop and refine EMIR runsets, stimulus methodologies, and reporting dashboards to improve predictability and reduce iterations • Build and maintain EMIR analysis flows and automation infrastructure for efficient multi-corner analysis • Deliver clear, actionable root-cause analysis and mitigation guidance at both block and full-chip levels Basic Qualifications: • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field • 8+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below) • Deep expertise in power grid design, PDN analysis, and EM reliability mitigation, including static and dynamic IR methodologies and foundry sign-off criteria • Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX • Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis Preferred Qualifications: • Master's degree in Electrical Engineering or a related field • Power integrity experience on high-speed SerDes, Ethernet PHY, or PCIe designs • Package-level power delivery analysis / co-simulation, including advanced packaging or multi-die integration exposure • Experience building EMIR methodology infrastructure that scales across multiple concurrent tapeout programs Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligi