Jobs / United States / Astera Labs INC
Principal Physical Design Engineer, Methodology
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Principal Physical Design Engineer - Methodology , you will define, develop, and maintain the reusable physical design flows and automation infrastructure that the entire PD team relies on. You will build the RTL-to-GDSII flow, integrate and qualify tools from multiple vendors (Cadence and Synopsys), and continuously improve PPA and schedule predictability across all programs. You are the force multiplier scaling the team's capabilities and enabling faster, better tapeouts. This role is fully on-site at our San Jose, CA location. Key Responsibilities: • Flow & Methodology Ownership • Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR • Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC) • Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability • Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements • Automation & Scale • Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage • Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs • Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization • Standards, Quality & Enablement • Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs • Support physical design engineers with flow issues, tool configurations, and methodology guidance • Drive adoption of flow improvements across the team, including training and documentation Basic Qualifications: • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred. • 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below) • Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows • Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains • Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation • Experience building and maintaining multi-corner/multi-mode analysis infrastructure • Understanding of foundry design rules, technology files, and enablement kit integration • Ability to work independently with strong prioritization and a results-driven mindset Preferred Qualifications: • Knowledge of agentic AI solutions for EDA automation • Experience with CI/CD integration for physical design flows • Familiarity with compute farm management and job schedul