Jobs / United States / Astera Labs INC
Principal Product Applications Engineer – Memory & CXL
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles26 certified filings for “Tech Lead Firmware Engineer” (Electronics Engineers, Except Computer) in CA: $157k–$216k, median $165k. Most were filed at wage level II (42%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Product Applications Engineer – Leo About the Role Astera Labs is looking for a Principal Product Applications Engineer to support the deployment of our Leo Smart Memory Controller and Extender solutions in next-generation server, AI, and datacenter platforms. This role sits at the intersection of memory architecture, system integration, hardware/software debug, and customer engineering . You will work directly with customers and Astera Labs engineering teams to bring up platforms, troubleshoot complex memory and system issues, support product development, and drive solutions from initial integration through production. We are looking for an experienced engineer with strong DDR/DRAM and memory subsystem expertise who enjoys solving complex system-level problems and working with customers. Experience with CXL and related high-speed technologies is highly relevant. Firmware or platform software experience is valuable, but not required. What You Will Do • Serve as a technical point of contact for customers integrating Leo products into server, AI, and datacenter platforms. • Support customer platform bring-up, integration, debug, and production deployment. • Troubleshoot complex memory, hardware, system, and software interactions. • Analyze DDR and memory subsystem behavior, including initialization, training, configuration, performance, and error handling. • Work with customers and internal engineering teams to isolate root causes and drive technical issues through resolution. • Collaborate with hardware, firmware, validation, systems, and product engineering teams on customer issues and new product capabilities. • Review system architectures, schematics, logs, debug data, and technical documentation to identify and resolve issues. • Support integration and debug of CXL, PCIe, and other high-speed interfaces. • Translate customer requirements and technical issues into actionable engineering requirements and product feedback. • Create technical documentation, application notes, debug reports, and customer-facing technical material. • Participate in customer technical reviews, platform bring-up activities, and product demonstrations. • Help identify opportunities to improve product functionality and customer deployment experience. What You Bring Required • Significant hands-on experience with DDR/DRAM and memory subsystems in server, datacenter, SoC, controller, semiconductor, or related computing environments. • Strong understanding of memory architecture and the interaction between memory, CPUs/SoCs, controllers, and platform components. • Experience with memory bring-up, debug, validation, integration, or system-level troubleshooting . • Ability to analyze complex technical problems and work across multiple engineering disciplines to identify root cause. • Experience working with hardware, systems, validation, product, or customer engineering teams. • Strong technical communication skills, including the ability to explain complex m