Jobs / United States / Astera Labs INC
Principal Product Technical Leader — AEC/SCM
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles1 certified filing for “Director of Product Management” (Sales Engineers) in CA: $200k–$200k, median $200k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. The pay stated here ($160,000 USD) is below what this employer usually pays sponsored hires for this role. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a hands-on Principal Product Technical Leader to drive product integration for Active Electrical Cables (AECs) and Smart Cable Modules (SCMs) used in rack-scale AI infrastructure. You will serve as a technical owner across high-speed silicon and retimers, firmware, PCB or flex circuitry, cable assemblies, connectors, mechanical and thermal design, signal integrity, validation, manufacturing, and customers. You will translate system and customer requirements, engineering data, and field feedback into reliable, production-ready products. This is an individual-contributor role: you will lead complex technical investigations, resolve cross-domain issues, strengthen product readiness, and improve repeatable integration and debug practices. You should bring deep expertise in at least one relevant discipline and working knowledge across adjacent domains. Key Responsibilities Product integration and validation • Define product-level interfaces, integration plans, risks, validation checkpoints, and readiness criteria from design through production release. • Influence architecture and design decisions early, finding creative, practical solutions to tradeoffs across signal integrity, retimer and firmware integration, power, thermal performance, mechanical constraints, manufacturability, cost, and schedule. • Lead product-level electrical compliance and system validation for AEC/SCM products, including channel performance, eye margins, jitter, equalization, link training, BER, interoperability, and resolution of system-level issues. • Direct and review AEC/SCM hardware validation, including board-level probing, circuit verification, functional testing under nominal, corner, mechanical, and environmental conditions, and reliability/failure analysis; ensure results are correlated to design requirements and corrective actions are driven to closure. • Drive root-cause analysis for issues spanning silicon, firmware, hardware, SI, mechanical, thermal, test, and manufacturing teams. Production readiness and technical execution • Partner with NPI, manufacturing, quality, and operations teams to transition products from development into volume production. • Drive DFM/DFA/DFT reviews, production-test development, test-coverage improvements, yield analysis, and manufacturability feedback. • Own technical investigations and corrective actions for complex failures, process excursions, production escapes, and field issues. • Establish clear product specifications, issue-tracking practices, technical reports, and readiness reviews. Customer and cross-functional leadership • Provide technical direction during customer bring-up, interoperability testing, platform qualification, and escalations. • Collaborate with applications and customer engineering teams to resolve design-in challenges and translate field feedback into product improvements. • Lead cross-functional design and integration reviews across hardware, firmware, SI, mechanical,