Jobs / United States / Astera Labs INC
Principal Silicon Validation Engineer
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles11 certified filings for “Tech Lead System Validation Engineer” (Industrial Engineers) in CA: $155k–$176k, median $170k. Most were filed at wage level IV (55%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance. Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs. Basic Qualifications: • Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred. • ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision. • Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! • Proven track record solving problems independently, preferably as a tech lead • Required experience • Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet • Strong problem-solving skills, ability to solve problems independently • Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling • Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration • Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA Preferred Experience: • Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels • Familiarity with PCIe or Ethernet especially Electrical Compliance sections • Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces • Working knowledge of C or C++ for embedded FW • Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling • Working knowledge of common serial data specifications such as I2C, SPI, etc • Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. • Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues The base sal