Jobs / United States / Astera Labs INC
Senior ATE Test Engineer
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles26 certified filings for “Tech Lead Firmware Engineer” (Electronics Engineers, Except Computer) in CA: $157k–$216k, median $165k. Most were filed at wage level II (42%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
Or apply yourself on the official page →
Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview We are looking for Senior ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. This is an opportunity to contribute hands-on technical expertise within Astera Labs’ hyper-growth connectivity business and help deliver purpose-built solutions that scale with the demands of rack-scale AI systems. Basic Qualifications • Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred. • ≥2 year experience releasing complex SoC/silicon products to high volume manufacturing. • Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc. • Professional attitude with ability to execute on multiple tasks with minimal supervision. • Strong team player with good communication skills to work alongside a team of high caliber engineers. • Entrepreneurial, open-mind behavior and can-do attitude. Required Experience • Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms. • Collaboration with design team to define test strategy, create and own test plan. • Tester platform selection, design, and development of ATE hardware for wafer sort and final test. • Familiar with high-speed load board design techniques. • Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality. • Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests. • Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc. • Expertise in production test of high speed SerDes operating at 16Gbps and higher. • Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug. • Experience with lab equipment including protocol analyzers and oscilloscopes. • Experience with using Advantest 93k ATE platform. • Proficiency in, at least, one modern programming language such as C/C++, Python. Preferred Experience • Fluent in data processing using high level programming languages. • Experience in running External loopback at wafer sort. • Familiarity with modern databases Salary range is $135,500 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse