Jobs / United States / Astera Labs INC
Senior Manager, Digital Design
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives. This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems. Key Responsibilities • End-to-End Chip Development • Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment. • Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability. • Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations. • RTL Quality and Tape-Out Readiness • Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out. • Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle. • Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams. • Team and Cross-Functional Leadership • Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration. • Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution. • Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership. Basic Qualifications • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. • Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations. • 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design. • Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity. • Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality. • Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations. Preferred Qualifications • Expertise in RTL quality methodologies,