Jobs / United States / Astera Labs INC
Senior Principal Digital Design Engineer
Astera Labs INC · 🇺🇸 San Jose, CA
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions. Key Responsibilities • Architecture & Technical Leadership • Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines • Establish architectural standards and best practices that scale across the design organization • Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area • Design Execution & Ownership • Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up • Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies • Own accountability for design quality, schedule, and successful production delivery • Cross-Functional Collaboration • Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues • Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up • Work with firmware and software teams to optimize hardware-software interfaces • Mentorship & Process Excellence • Mentor and develop junior and senior engineers, elevating team technical capabilities • Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure • Contribute to organizational knowledge sharing and technical reviews Basic Qualifications • Bachelor's degree in Electrical Engineering or equivalent • 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets • Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure • Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar • Production experience with advanced CMOS nodes (≤7nm) • Proficiency with Cadence and/or Synopsys digital design flows • Track record of delivering multiple high-performance designs to production Preferred Qualifications • Maste