Jobs / United States / Astera Labs INC
Senior Principal Test Engineer
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles26 certified filings for “Tech Lead Firmware Engineer” (Electronics Engineers, Except Computer) in CA: $157k–$216k, median $165k. Most were filed at wage level II (42%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal Test Engineer to serve as a technical authority for test engineering across complex mixed-signal silicon and high-speed connectivity products. You will define Test strategies for SCM High Volume Manufacturing and Validation Boards shipped to customer development and own execution from early product engagement through high-volume manufacturing. This role is central to delivering reliable, scalable connectivity for rack-scale AI infrastructure. You will influence product quality, coverage, yield, test cost, and time to market while partnering with design, DFT, product engineering, operations, and manufacturing teams in a fast-moving, hyper-growth environment. Key Responsibilities • Test Strategy and Product Ownership • Define and own comprehensive test strategies, specifications, and plans from product definition through high-volume production. • Establish coverage, quality, yield, test-time, and cost objectives, and drive measurable improvements across the product lifecycle. • Partner with design and product engineering teams to identify testability requirements and make effective design-for-test tradeoffs. • Architect tester solutions and guide development of Tester HW design to meet specific and roadmap of products • Validate Tester Designs and characterize before implementing into Mass Production. • Apply understanding of physical-layer behavior to investigate failures, interpret lab and production data, and resolve complex performance issues. • Lead root-cause analysis and yield improvement using protocol analyzers, oscilloscopes, manufacturing data, and structured failure analysis. • Technical Leadership and Cross-Functional Execution • Serve as a senior technical advisor across test, DFT, design, operations, quality, and external manufacturing organizations. • Establish best-known methods, scalable test processes, and automation practices that improve engineering effectiveness and manufacturing readiness. • Mentor engineers, influence technical decisions, and communicate risks, tradeoffs, and recommendations to cross-functional stakeholders. Basic Qualifications • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. • 12–20 years of experience in Test engineering or Product Engineering from development through high-volume manufacturing. • Strong experience developing custom test solutions for high-speed, mixed-signal products for high volume manufacturing. • Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB. • Experience with Test SW development, production debug, and test-time optimization. • Proven experience developing and designing custom Test Hardware for PCBA High volume manufacturing. Preferred Qualifications • Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field. • Experience with Electrical HW board design on complex Test HW implement