Jobs / United States / Astera Labs INC
Tech Lead Engineer, Design Verification
Astera Labs INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Astera Labs INC paid sponsored hires in similar roles14 certified filings for “Tech Lead Design Verification Engineer” (Electrical Engineers) in CA: $160k–$218k, median $206k. Most were filed at wage level IV (70%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Astera Labs INC
The US Department of Labor certified 63 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 10 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Astera Labs INC →
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. Within CCE2, you will lead meaningful verification challenges from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver highly reliable PCIe and UALink connectivity products that keep AI accelerators, memory, and compute resources operating at scale. Key Responsibilities • Verification Strategy and Planning • Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements. • Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality. • Review designs and verification plans with architecture and RTL teams to identify corner cases early. • Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics. • Environment Development and Execution • Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models. • Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink , and UCIe behavior. • Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration. • Partner with RTL and firmware teams to refine interfaces, improve observability, and resolve functional issues. • Coverage, Quality, and Silicon Readiness • Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones. • Develop regression strategies and automation to improve test quality, turnaround time, and failure triage. • Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness. • Communicate verification status, risks, and recommendations to technical stakeholders and project leadership. Basic Qualifications • Bachelor’s degree in Electrical Engineering , Computer Engineering, or a related technical field. • 5–8 years of experience in design verification for complex ASICs or SoCs. • Hands-on experience with SystemVerilog and UVM-based verification environments. • Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models. • Familiarity with simulation, waveform-debug, regression, and coverage tools. • Strong technical leadership, debugging, communication, and collaboration skills in a fast-paced product development environment. Preferred Qualifications • Master’s degree in Electrical Engineering , Computer Engineering, or a related field