Tech Lead, STA

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About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Tech Lead STA Engineer Location - Hyderabad Experience - 6-14 years Role Overview Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry. This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you'll have the ownership, influence, and tooling to do the best work of your career. Key Responsibilities • Full-Chip STA Signoff & Timing Closure • Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs • Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout • Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level • Methodology & Flow Development • Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization • Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing • Establish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks • Cross-Functional Technical Leadership • Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout • Review and sign off on block-level timing handoffs, ensuring consistency between block and top-level closure • Collaborate with low-power design teams on UPF/CPF, multi-voltage, and clock-gating timing implications • Mentorship & Technical Strategy • Mentor STA engineers and review timing reports, ECOs, and signoff collateral • Drive root-cause analysis of silicon timing issues and feed learnings back into methodology • Influence tool selection, EDA vendor engagements, and STA roadmap for future products Basic Qualifications • Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field • 6+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs • Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below) • Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development • Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing • Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis Preferred Qualifications • Master's degree in Electrical Engineering or related field • Experience with

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