Jobs / United States / Renesas Electronics America INC

Renesas Electronics America INC

Director, Digital Design & Verification

Chandler, Arizona, US Posted 21 days ago

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

• Deliver high-quality digital design and verification across all programs (schedule, performance, silicon success)  • Achieve predictable execution with early risk identification and strong mitigation frameworks  • Improve first-pass silicon success rate through disciplined verification and robust design practices  • Enable faster time-to-market through reuse, automation, and methodology standardization  • Build the site into a self-sufficient digital & verification hub, reducing dependency on external sites    Responsibility   • Own end-to-end digital design and verification delivery for the site  • Establish and drive verification strategy (simulation, formal, AMS/DMS) as a coherent, evolving plan  • Own digital architecture quality, including system control logic, FSM design, FW interfaces, and IP reuse  • Define and enforce sign-off criteria, including coverage, closure metrics, and design quality gates  • Align digital and verification execution with product roadmap, customer requirements, and business priorities    Direction (Strategic Leadership)  • Define a clear multi-year vision for digital and verification capabilities at the site  • Translate business and product strategy into technical roadmap and capability investments  • Drive adoption of best-in-class methodologies, tools, and automation frameworks  • Continuously adapt strategy based on execution gaps, competitive pressure, and program risk  • Elevate the role from task execution to systemic impact and organizational leverage  Alignment (Influence & Collaboration)  • Lead cross-functional alignment with analog, system, FW, product, and test teams  • Act as the primary the site interface for digital and verification in global reviews  • Align with other sites on IP reuse, methodology standardization, and sign-off practices  • Build strong partnerships with product line managers to ensure design meets system and market needs  • Ensure seamless integration across global teams for multi-site program delivery  Core Responsibilities  Technical & Architecture Leadership  • Guide architecture decisions for digital control systems, power management FSMs, and system interfaces  • Ensure robust design practices across:   • RTL quality (coding standards, lint, CDC)  • Timing closure (STA, constraints)  • DFT/scan and test readiness  • Drive design reuse strategy to improve productivity and consistency  Verification Excellence  • Establish a world-class DV capability including:   • Coverage-driven verification  • SystemVerilog/UVM environments  • Formal verification where applicable  • AMS/DMS co-simulation for mixed-signal validation  • Define verification plans that ensure full coverage and sign-off confidence  • Drive automation and regression efficiency to scale execution  Execution & Delivery  • Own delivery across all digital and DV activities with clear accountability  • Drive execution rigor:   • Milestone planning  • Risk tracking and mitigation  • Transparent status reporting  • Ensure consistent on-time tape-out with high-quality silicon  Organization & Talent  • Build and scale a high-performing digital & verification team  • Define roles, expectations, and career progression aligned with job leveling frameworks  • Develop technical leaders and mentors to increase organizational leverage  • Drive hiring, retention, and capability growth aligned with site strategy   Methodology & Continuous Improvement  • Institutionalize standardized design and verification flows  • Drive continuous improvements in:   • Productivity (reuse, automation)  • Quality (coverage, bug escape reduction)  • Efficiency (cycle time reduction)  • Promote a culture of data-driven decision making and engineering rigor  Expected Impact  •

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