Jobs / United States / Tenstorrent USA INC
Performance Architect, CPU Cluster
Tenstorrent USA INC · 🇺🇸 Austin, Texas, United States; Santa Clara, California, United States; Santa Clara, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 47 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Tenstorrent USA INC
The US Department of Labor certified 47 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Tenstorrent USA INC →
About the role
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a CPU Cluster Performance Architect to help shape the performance and scalability of our next-generation CPUs. You’ll focus on how multiple CPU cores work together as a cluster — from cache hierarchies and coherent interconnects, to memory bandwidth and overall system behavior. This is a hands-on architecture role for someone who enjoys using performance models and simulation to understand bottlenecks, explore tradeoffs, and influence decisions early in the design process. You’ll work closely with CPU architects, RTL designers, software and compiler teams, and system architects to understand workload behavior and turn performance insights into architectural improvements. If you enjoy looking at the entire cluster and how performance scales across cores, memory systems, and chiplets, this is an opportunity to have a significant impact. This role is remote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are • You have a strong foundation in CPU microarchitecture and performance, with an understanding of how cores, caches, interconnects, and memory systems interact. • You enjoy using modeling, simulation, and workload analysis to understand cluster-level performance bottlenecks and scaling challenges. • You’re comfortable moving between detailed microarchitecture and broader system-level questions around latency, bandwidth, quality of service, utilization, and scalability. • You’re analytical and hands-on, with the ability to turn large amounts of performance data into clear architectural recommendations. • You’re a strong communicator who enjoys working across architecture, RTL, compiler, software, and system teams. What We Need • Analyze and optimize CPU cluster performance, including cache hierarchies, interconnects, coherence, and memory access behavior. • Build and use performance models and simulation environments such as Gem5 or equivalent to evaluate architectural concepts and identify performance opportunities. • Study real workloads to understand bottlenecks related to cache misses, coherence traffic, memory bandwidth, latency, contention, and core-to-core communication. • Lead architectural tradeoff studies across performance, scalability, bandwidth, latency, power, and implementation complexity. • Collaborate with CPU, cache, interconnect, memory, software, and system architects to translate performance analysis into concrete design decisions. What You Will Learn • How to architect, model, and optimize a multi-core CPU cluster from early performance exploration through implementation and silicon. • How cache coherence, interconnects, memory hierarchy, and core architecture interact to determine overall system performance. • How to model and reason about scaling across cores, including contention, bandwidth limits, latency, and workload behavior. • How architectural decisions at the cluster level translate into real-world application p