Principal RTL Design Engineer

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About the role

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the team The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design. About the role SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This is a senior individual contributor role where you'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, owning the power, performance, and area trade-offs along the way. Frequency targets are aggressive, so how you pipeline a datapath and where you spend area to buy timing are essential aspects of the role. Responsibilities • Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems • Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle • Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring • Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent • Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures • Work with architects and software teams to prototype and evaluate features that improve application-level performance • Drive AI, automation, and new EDA tool methodologies into the design flow • Set the technical bar in design reviews and mentor design engineers Required Qualifications • B.S. in Electrical Engineering, Computer Engineering, or Computer Science • 7+ years of industry experience in ASIC RTL design • Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent • High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets • Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures • Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC • Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team • Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows • Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers •

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