Jobs / United States / Sambanova Systems INC
Senior Principal Hardware Emulation Engineer
Sambanova Systems INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 23 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 4 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Sambanova Systems INC paid sponsored hires in similar roles6 certified filings for “Senior Hardware Engineer” (Electronics Engineers, Except Computer) in CA: $157k–$175k, median $158k. Most were filed at wage level II (83%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Sambanova Systems INC
The US Department of Labor certified 23 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 4 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Sambanova Systems INC →
About the role
SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the team The emulation team builds the pre-silicon model of SambaNova's RDU that the software, architecture, and verification teams depend on. About the role SambaNova is looking for a Senior Principal Engineer to build and own the hardware emulation models for our next-generation Reconfigurable Dataflow Unit — the silicon behind our AI workload acceleration systems. Emulation is a development platform here, not a checkbox. Our software teams bring up drivers, runtime, and compiler against the emulation model months before silicon. Our architects measure performance on it. Our verification team runs on it to get through scenarios that simulation cannot reach in useful time. When the model is fast, accurate, and available, three organizations move faster; when it is not, they wait. Building that model is the core of the job. You will work shoulder to shoulder with the RTL design team to keep the design emulation-compliant, decide where a vendor model will do and where you need to write a custom one, and own the automation that keeps the platform running tests continuously rather than by hand. This is a senior individual-contributor role, and much of its leverage comes through other teams: you will be the person design, verification, and software engineers consult on what emulation can and should do, and the one who holds our emulator vendors to account. div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8"> _*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown"> Responsibilities Build the models • Develop the emulation model for each new RDU generation: high-performance transactors, behavioral models, and memory models in SystemVerilog and C/C++ • Partner with the RTL design team to keep the design emulation-compliant: review RTL and IP for constructs that will not map cleanly to the emulator, and close the gaps by substituting vendor emulation models or hand-coding custom models where no vendor model exists • Own model fidelity: make sure substituted and custom models track design intent closely enough that software, performance, and verification results can be trusted • Influence design decisions upstream so emulation-readiness is designed in rather than worked around Own the platform, flows, and automation • Own the emulation environment architecture: build and runtime flows, partitioning, compile strategy, clocking, and memory configuration for each chip generation • Build and own the workflows that automate emulation testing on the hardware: job scheduling, regression launch, failure triage, and results reporting, so the platform runs continuously without manual babysitting • Own throughput and capacity: profile and remove bottlenecks in models, transactors, and te