Jobs / United States / Sambanova Systems INC
Senior Validation & SI Correlation Engineer
Sambanova Systems INC · 🇺🇸 San Jose, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 23 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 4 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Sambanova Systems INC paid sponsored hires in similar roles8 certified filings for “Principal Engineer” (Computer and Information Research Scientists) in CA: $175k–$190k, median $183k. Most were filed at wage level II (100%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Sambanova Systems INC
The US Department of Labor certified 23 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 4 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Sambanova Systems INC →
About the role
SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the Role SambaNova Systems is redefining what’s possible in AI infrastructure—and the hardware that powers it has to be flawless. As a Senior Hardware Validation & SI Correlation Engineer, you will own the technical bridge between simulation and silicon, ensuring that every high-speed link, control bus, and power rail in our next-generation AI server systems performs without compromise. This is a high-impact, highly visible role that blends deep Signal Integrity (SI) expertise with rigorous system-level hardware validation. You will work at the frontier of AI compute—validating PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces on systems pushing the limits of what data center hardware can do. If you thrive in a fast-paced lab environment, love digging into root cause, and want your work to directly accelerate the future of AI, this role is built for you. What You’ll Do SI Modeling & Measurement Correlation • Drive the correlation between pre- and post-layout SI simulations and physical lab measurements, closing the loop between theory and hardware reality. • Quantify simulation-vs-measurement gaps for PCIe Gen5/6, DDR5, and 112G/224G Ethernet using S-parameters, TDR, and eye diagram analysis. • Develop and refine EM models for PCB discontinuities, high-speed connectors, and vias using Ansys HFSS, Cadence Sigrity, or equivalent tools. • Investigate discrepancies caused by manufacturing tolerances, material properties (Dk/Df), or de-embedding inaccuracies and drive them to resolution. System-Level Electrical Validation • Lead validation of housekeeping and control buses—I2C, SPI, eSPI, UART, SMBus—ensuring protocol compliance and robust timing margins. • Validate complex power-on/off sequences and correlate VR control loop simulations with physical transient response and ripple measurements. • Ensure reliable operation of sideband signals, reset logic, and BMC hardware interfaces under intensive AI workloads. • Work cross-functionally with SI, Power Integrity (PI), and Firmware teams to resolve system-hang and link-training failures rooted in electrical noise or power instability. Test Methodology & Automation • Author comprehensive Hardware Validation Plans (HVP) with full coverage of critical electrical test points. • Build Python-based automation scripts to drive data collection from VNAs, BERTs, and oscilloscopes—accelerating validation throughput and repeatability. What You’ll Bring Required Qualifications • B.S. or M.S. in Electrical Engineering (M.S. preferred). • 10+ years of experience in high-speed digital design or hardware validation within a data center, systems architecture, or server bring-up environment. • Expert-level proficiency in SI/EM tools: Ansys HFSS/SIwave, Cadence Sigrity/Allegro, or Keysight ADS. • Hands-on mastery of high-bandwidth real-time oscilloscopes, VNAs, and logic analyzers. • Deep knowledge of high-speed protocol physical layers (PCIe, IEEE 802.3) and low-speed control buses (I2C, SPI). • Strong fundamentals in digital circuit design, debug, and computer architecture. • Familiarity with the unique power and thermal challenges of high-density AI clusters—including 4