Jobs / United States / Neuralink Corp
Digital Verification Engineer
Neuralink Corp · 🇺🇸 South San Francisco, California, United States
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 21 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 2 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Neuralink Corp paid sponsored hires in similar roles3 certified filings for “Physical Design and Verification Engineer” (Electrical Engineers) in CA: $134k–$193k, median $165k. Most were filed at wage level II (33%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
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Sponsor Radar — Neuralink Corp
The US Department of Labor certified 21 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 2 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Neuralink Corp →
About the role
About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP) . We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Required qualifications : • Minimum 3 years of experience in digital ASIC verification. • Excellence in SystemVerilog. • Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell • Experience with code coverage and regression setup. • Bachelor's degree in a technical field OR equivalent experience. Preferred qualifications : • Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools. • Experience on building test benches, testing, and debugging for a complex system-on-chip. • Experience in formal verification. • Functional modeling experience and logic verification with SystemVerilog, SystemC/C++. • Experience with IEEE-1801 (UPF) based design simulation flows • Experience with low power gate level simulations • Exposure with low power formal verification flows • Strong hands-on experience in verification methodologies such as UVM • Knowledge of ARM/RISC-V processor, AMBA bus • Knowledge of power aware verification • Experience with FPGA/emulation • Experience with lab system bring up, writing diagnostic, and lab debugging Expected Compensation: The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range: $131,000 — $243,000 USD What We Offer: Full-time employees are eligible for the following benefits listed below. • An opportunity to change the world and work with some of the smartest and most talented experts from different fields • Growth potential; we rapidly advance team members who have an outsized impact • Excellent medical, dental, and vision insurance through a PPO plan • Paid holidays • Commuter benefits • Meals provided • Equity (RSUs) *Temporary Employees & Interns excluded • 401(k) plan *Interns initially excluded until they work 1,000 hours • Parental leave *Temporary Employees & Interns excluded • Flexible time off *Temporary Employees & Interns excluded