Jobs / United States / Nvidia Corporation
Low-Power Feature Validation & Bring-Up Engineer
Nvidia Corporation · 🇺🇸 US, CA, Santa Clara
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 394 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Nvidia Corporation paid sponsored hires in similar roles701 certified filings for “Engineer Senior Systems Software” (Software Developers) in CA: $173k–$214k, median $190k. Most were filed at wage level IV (82%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Nvidia Corporation
The US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 394 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Nvidia Corporation →
About the role
NVIDIA Silicon Co-Design Group is looking for a versatile engineer to help redefine how low-power silicon validation and system bring-up are developed for next-generation AI and accelerated computing platforms. Our team sits at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization. We build the methodologies, infrastructure, and workflows that take low-power features from architectural intent through silicon bring-up and into production readiness. This role is about scaling low-power validation using AI-powered analytics, intelligent automation, telemetry pipelines, and modern debug workflows. You will help transform how power validation, workload characterization, feature correlation, and silicon debug are accomplished across product generations. The payoff is that the systems, tooling, and methodologies you help build will directly influence the power efficiency, stability, and production readiness of NVIDIA products shipped at scale worldwide. What You'll Be Doing: • Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies. • Build intelligent workload characterization frameworks that use telemetry, behavioral clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier in the development cycle. • Define the instrumentation, counters, telemetry frameworks, and firmware hooks needed to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout. • Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using sophisticated automation, data-driven validation methodologies, and generative AI-assisted debug techniques. • Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation. • Partner closely with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to build scalable validation pipelines, intelligent dashboards, and modern engineering workflows for next-generation silicon platforms. • Support manufacturing and customer-facing teams in resolving production and feature issues using telemetry-powered insights, automated analytics, and scalable debug methodologies. • Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from early architecture definition through silicon bring-up, validation, and product release. What We Need to See: • BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience. • 10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization. • Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, power/performance tradeoffs, and system-level validation methodologies. • Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation, debug, or productization. • Strong EE fundamentals, including digital design, computer architecture, power analysis, statistics, and scripting/programming skills. • Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation. • Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, telemetry analytics, or data-driven debug infrastructure. Ways to Stand Out from the crowd: • Experience applying AI/ML or LLM technologies to silicon validation, telemetry analytics, workload optimization, or d