Jobs / United States / Nvidia Corporation

Nvidia Corporation

Senior Mixed Signal Circuit Design Engineer

2 Locations Posted today

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Nvidia Corporation paid sponsored hires in similar roles701 certified filings for “Engineer Senior Systems Software” (Software Developers) in CA: $173k–$214k, median $190k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Nvidia Corporation paid sponsored hires in similar roles
701 certified filings for “Engineer Senior Systems Software” (Software Developers) in CA: $173k–$214k, median $190k. Most were filed at wage level IV (82%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL. You will have hands on experience taking innovative integrated circuit designs at data rates of 50Gbps and higher from concept through silicon characterization. What you will be doing: • Define circuit requirements and complete design from schematic, layout, and verification to characterization. • Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. • Take responsibility for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. • Optimize circuit to meet the specifications for system performance. • Work with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. • Provide support for post-silicon bring-up and debugging. What we need to see: • Master of Science or foreign equivalent degree in Electrical Engineering, Computer Engineering or related field with strong analog design background. • 3+ years analog design experience in industry. • CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET); Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) • Experience in crafting test bench environments for component and top level circuit verification; Behavioral modeling of analog and digital circuits. • Strong debugging and analytical skills; Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. • Strong communication skills and ability & desire to work as a great teammate are huge plus.

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