Sponsorship verdict
Sponsorship possible
One solid signal, not two. Worth applying, and worth asking about sponsorship early.
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✓
Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
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The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
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No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
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✓
What Intel Corporation paid sponsored hires in similar roles11 certified filings for “SoC Design Engineer” (Architectural and Engineering Managers) in TX: $160k–$224k, median $192k.
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✓
Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Employer is on a government sponsor record
- The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
- No salary bar for this route
- H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles
- 11 certified filings for “SoC Design Engineer” (Architectural and Engineering Managers) in TX: $160k–$224k, median $192k. Most were filed at wage level II (36%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.
About the role
Job Details:
Job Description:
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.
Life at Intel
In this role you will be part for the Server SoC Design Validation team, working on next-generation Xeon server product SOCs and IPs.
Who You Are:
Your responsibilities include but are not limited to:
• Performs functional logic verification and emulation validation of an integrated SoC to ensure design will meet specifications.
• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
• Replicates, root causes, and debugs issues in the pre-silicon environment.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
Behavioral traits that we are looking for:
• Self-reliance in taking an issue to closure with internal and external partners.
• Takes ownership of assigned tasks.
• Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market.
Qualifications:
This is an entry-level position and will be compensated accordingly. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Master's degree in electrical or computer science, Engineering or related field.
Related coursework/technical experience in/with:
• 10+ months experience with Silicon Design and/or Validation/Verification.
• 10+ months experience with x86 Architecture.
• 10+ months experience with Design and validation experience with global domains (Reset, Clock, Fuse, GPIO, MPP)
Preferred Qualifications:
Knowledge and Experience with:
• Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
• Strong debug skills.
• Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer.
• UVM/SV constrained-random coverage-based design verification and Formal Verification methodology.
• Complete verification life cycle (verification architecture, test plan,
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