Jobs / United States / Hewlett Packard Enterprise Company

Hewlett Packard Enterprise Company

Senior ASIC Design Verification Engineer - Slingshot

3 Locations Posted today

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Hewlett Packard Enterprise Company paid sponsored hires in similar roles1 certified filing for “Senior ASIC Verification Engineer” (Computer Hardware Engineers) in NC: $203k–$203k, median $203k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Hewlett Packard Enterprise Company paid sponsored hires in similar roles
1 certified filing for “Senior ASIC Verification Engineer” (Computer Hardware Engineers) in NC: $203k–$203k, median $203k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

Senior ASIC Design Verification Engineer - Slingshot    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. In this case, Chippewa Falls, WI, Fort Collins, CO or Bloomington, MN. Who We Are Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. About the Team and the Project Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems ( https://www.hpe.com/us/en/compute/hpc/slingshot-interconnect.html ). As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own significant verification scope, set technical direction for a block or subsystem, and help shape how our team applies emerging agentic AI workflows to solve complex engineering problems. We are looking for engineers who want to work at the leading edge of high-performance interconnects for HPC and AI, who enjoy mentoring, and who want real influence over verification methodology rather than a narrowly defined test-writing role. Job Description In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews. Responsibilities • Follow and help define the team's design verification methodology. • Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus. • Plan and implement block and integration level scoreboards and checkers to verify functional behavior. • Write and analyze functional coverage, providing input to block level milestones. • Triage regression failures and identify logic bugs, while driving bug closure. • Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process. • Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence. • Participate in and provide input on the process for selection of future technical leaders. • Drive VLSI innovation and integration of

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