Jobs / United States / Hewlett Packard Enterprise Company

Hewlett Packard Enterprise Company

ASIC Design Engineer

Sunnyvale, California, United States of America Posted today

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Skills this job asks for

NetworkingCustomer successLeadershipPython

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Hewlett Packard Enterprise Company paid sponsored hires in similar roles1 certified filing for “Senior ASIC Verification Engineer” (Computer Hardware Engineers) in NC: $203k–$203k, median $203k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Hewlett Packard Enterprise Company paid sponsored hires in similar roles
1 certified filing for “Senior ASIC Verification Engineer” (Computer Hardware Engineers) in NC: $203k–$203k, median $203k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

ASIC Design Engineer    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: HPE Networking is a leading provider of advanced routers and switches for the internet .   We keep the world connected with speed, reliability, security, and ease of use.   At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon   die .   We build   cutting edge   networking chips used to build   our   world-class routers and switches.    Bring your passion and there are no boundaries to what you can   accomplish   here. We are like   a start -up in a big company. Year after year, our group builds the most powerful and highest density networking chips.    As part of our fast-paced   silicon   group, you will   become an expert   in   building   high-speed   ASICs , from specifications to final netlist.   We give you opportunities to work on complex   modules and subsystems   where you can challenge yourself and grow.   Open communications, empowerment, innovation,   teamwork,   and customer success are the foundations of   team   culture .   Thus, you set your own limits for learning,   achievements,   and rewards.    Responsibilities:   • You will start with a functional specification of a module and produce a detailed micro-architecture   specification   that meets the power/area requirements .   • You will i mplement the design using Verilog or System Verilog    • W rite functional coverage/SVA   to help verification catch corner case   bugs.   • You will w ork with   the Physical   D esign team for   optimal   floorplan and   t iming closure . You will   identify   and f ix timing in RTL to meet the frequency target.    • Work with the Verification team t o make sure your block is fully   validated .    • You will have opportunities to improve   leadership   skills   by providing   mentoring/ guidance to new college-grad engineers and   interns.         Recommended skills   • Bachelor’s degree in Electrical Engineering   required   ( Master’s   strongly   desired ) with 4 +   years of relevant   experience.   • Strong analytical/problem solving skills.   • Knowledge of Computer Architecture/networking protocols through graduate level courses or   prior   work   is a plus.   • Strong coding skills in Verilog/System Verilog through courses /projects and   previous   work experience   is   desired.   • Knowledge of synthesis/lint   and other   state-of-the-art   EDA tools   is   desired.   • Excellent written and verbal   communications   skills   are   good to have.   • Knowledge of Perl/Python is a   plus. • Experience with AI agentic tools is a plus. Accessibility HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked h

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