Jobs / United States / Renesas Electronics America INC

Renesas Electronics America INC

Senior Principal Engineer

San Jose, CALIFORNIA, US Posted today

Apply on employer site ↗ Tailor my CV first Source: Company careers site

Optional: we can tailor a CV and cover letter for this job from your real experience first (the first one is free).

Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Renesas Electronics America INC paid sponsored hires in similar roles4 certified filings for “Staff System Engineer” (Electronics Engineers, Except Computer) in CA: $162k–$187k, median $168k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Renesas Electronics America INC paid sponsored hires in similar roles
4 certified filings for “Staff System Engineer” (Electronics Engineers, Except Computer) in CA: $162k–$187k, median $168k. Most were filed at wage level II (100%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

We are seeking a Power Design Engineer to lead the development of test vehicles supporting our high-current BCD (Bipolar-CMOS-DMOS) and low-voltage GaN power process and product portfolios. This role owns test vehicle definition, circuit and layout design, and characterization planning from concept through silicon bring-up, working closely with process development, product engineering, and applications teams. The ideal candidate has hands-on experience designing power devices and circuits at both the IC and module level, and is fluent in the power topologies these test vehicles are ultimately intended to support. Key Responsibilities • Define, design, and drive execution of test vehicles (TVs) for high-current BCD and LV GaN process technologies, including device test structures, scaled power stages, and full-function demonstration circuits. • Translate process capability targets and product roadmap requirements into test vehicle architecture and specifications. • Design and simulate power stage circuits (e.g., synchronous buck/boost, multiphase, half-bridge/DrMOS, gate drivers) used to validate device performance under realistic switching and thermal conditions. • Select and characterize power devices (LDMOS, trench MOSFETs, LV GaN HEMTs, Schottky/sync rectifiers) for inclusion in test structures, working with device/process engineering on layout-dependent tradeoffs (RDS(ON), Qg, breakdown voltage, SOA). • Perform IC-level layout and design for test structures, including parasitic-aware layout for switch nodes, current sensing, and gate drive paths. • Extend designs to module/package level as needed — co-design of power stages with packaging, magnetics, and PCB layout for evaluation boards and system-level test vehicles. • Develop test and characterization plans covering DC parametrics, switching performance, efficiency, transient response, and voltage/current stress margins (including switch-node ringing and abs-max validation). • Lead or support silicon bring-up, debug, and correlation of measured results against simulation and design targets. • Collaborate cross-functionally with process integration, reliability, product/applications engineering, and test engineering to close the loop from process split data to product-ready specifications. • Document design methodology, test vehicle results, and characterization data to support technology qualification and product development decisions. • Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related field. • 10+ years of hands-on design experience in power semiconductor devices, analog/power ICs, or power electronics. • Strong working knowledge of power conversion topologies (e.g., buck, boost, multiphase/interleaved converters, half-bridge, DrMOS/Intelli-Phase-style architectures) and how topology choices drive device requirements. • Solid understanding of power device physics and tradeoffs across BCD process technologies and GaN (particularly low-voltage GaN HEMTs) — including RDS(ON), switching loss, gate charge, breakdown/avalanche behavior, and thermal characteristics. • Demonstrated experience designing test structures or test chips/vehicles for process technology development (not just product design) — comfortable defining what a process node needs to prove out. • IC-level design and layout experience, including parasitic-sensitive layout practices for high-current switching nodes. • Experience taking designs beyond the die level to module, package, or board level (e.g., power module co-design, evaluation board layout, thermal/electrical co-design). • Proficiency with circuit simulation tools (SPICE or equivalent) and familiarity with device/TCAD simulation concepts. • Ability to interpret and specify absolute maximum ratings,

Apply on employer site ↗