Sponsorship verdict
No sponsorship evidence yet
No government record and no wording either way. Not a refusal: ask the recruiter.
-
?
No government sponsor record hereThis employer posted directly and does not match a government sponsor register.
-
?
The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
-
?
No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
-
✓
Confirmed live todayWhen a source last listed this job as open.
Details and sources
- No salary bar for this route
- H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.
Before you apply
Sponsorship unknown
No register record and no sponsorship wording in the posting. Worth asking the employer before investing significant time.
These come from the posting’s own wording. Read the original listing to confirm. See better-fit alternatives →
About the role
Senior FPGA Engineer – Systems Team
Cambridge, UK | Full-time | Permanent | Hybrid
Salary: £70,000 to £108,000, DOE
The salary range for this role is broad, as we are able to consider varying levels of experience. Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements.
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
Systems Engineering bridges the gap between Riverlane and its customers. They act as the primary technical interface for our customers’ engineers to guide them through product integration and help with troubleshooting complex quantum systems. They are key to securing design wins and driving product development.
As an FPGA Engineer, you will configure our Deltaflow Hardware to connect Quantum Computers to provide low-latency, high throughput systems that perform complex operations in a predictable and guaranteed way. You will use your knowledge and expertise to adapt the hardware to an ever-changing quantum control system to support scientists that are running quantum experiments.
This is a fantastic opportunity to join Riverlane’s team, that is developing the world’s most advanced quantum error correcting algorithms. The Riverlane team is a mix of mathematicians, physicists and engineers, working together on a range of exciting and cutting-edge projects.
What you will do:
Technical pre-Sales:
• Host Technical Workshops on Riverlane’s QEC Interface
• Evaluate Customers Control System and Data Communication requirements.
Integration On-Site: End-to-End System Deployment:
• Writing RTL to adapt to customers control systems and ensure data packets are received correctly.
• Work with Riverlane’s Quantum Application Team to design experiments to test the system.
• Benchmark and discover hardware latency limitations.
Troubleshooting and Debugging: Managing Customer Issues:
• Report issues and help replicate the setup with the QA team in Riverlane.
• Writing script to debug and trace faults
• Update verification environment and the test vectors based on data gathered from the experiments that were conducted.
Customer Advocacy: Voice of the Customer to Riverlane Product Team:
• Highlight the success, issues and trends on customer’s Quantum Systems
• Feedback key features that will be needed to win current and next generation products
What we need:
• Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)
• Experience in writing SystemVerilog or VHDL
• Proven professional experience in at least one of the following areas:
• Implementation of modern classical decoders on FPGA e.g. LDPC, turbo-codes;
• Implementation of Ethernet and High-Speed Protocols
• Implementation of customs protocols and st
View original listing ↗