Principal FPGA Emulation Engineer

About the Role Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power-control architectures pre-silicon — proving out control loops, catching RTL issues early, and de-risking tape-out. These FPGA platforms are emulation vehicles, not production hardware. Success is measured by how faithfully and how fast they reproduce the target silicon: functional equivalence to the golden ASIC RTL, real-time (or near-real-time) performance for closed-loop power and DSP validation, and deep visibility for pre-silicon debug. What You'll Do • Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA — advising on FPGA-ability and turning architectural intent into a working, real-time emulation platform. • Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design — handling clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state/bus conversion, and stubbing or modeling of analog/mixed-signal blocks. • Map designs onto the FPGA fabric to fit and to hit emulation speed — steering resource inference (DSP/multiplier slices, block vs. distributed memory), clocking, and pipelining so the design achieves the real-time performance the validation requires. • Build the real-time environment around the digital core: model or interface to the analog and power stages (ADC/DAC/PWM, gate drivers, plant/converter models), including hardware-in-the-loop with real or emulated power hardware where needed. • Develop deep pre-silicon debug and visibility — logic analysis, long-run waveform capture, triggering, and assertions — and enable firmware/software co-development ahead of silicon. • Define and continuously improve the emulation methodology, RTL/FPGA-ability guidelines, flows, and automation (TCL/Python). • Provide technical leadership: mentor engineers, lead reviews, and drive emulation and tooling decisions across the silicon and systems teams. Required Qualifications • Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs. • Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL. • Deep understanding of FPGA internal architecture and primitives — DSP/multiplier slices, block and distributed RAM, carry chains, and clocking — and a proven ability to map designs onto these resources to fit large ASIC RTL and reach real-time emulation performance (memory/SRAM macro mapping, DSP inference, clock-enable conversion, control-set and fanout management). • Hands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling. • Strong command of the full FPGA implementation flow — synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) — on large Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus. • Hardware bring-up and debug experience: in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug. • Proficiency scripting for automation (TCL, Python). • Demonstrated technical leadership — mentoring, reviews, and driving cross-team technical decisions. • BS or MS in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience). Preferred Qualifications • Real-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and