Senior Full-Chip RTL Integration Engineer

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! We are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team. In this role, you will be responsible for integrating complex IPs and subsystems into large-scale SoCs while ensuring design quality, verification readiness, and DFT compliance. You will work closely with Architecture, Design, Verification, DFT, and Physical Design teams to deliver high-quality silicon products in a collaborative and fast-paced environment. If you are a problem solver and highly motivated individual searching for a collaborative and exciting role, join us today! We encourage applicants with a history of proven success working in a multicultural and diverse environment. What you'll be doing: • Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration. • Work closely with Architecture, RTL Design, Verification, DFT, and Physical Design teams to drive system-level integration and design closure. • Perform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation. • Develop and carry out integration-level verification plans using SystemVerilog/UVM, debug simulation failures, and support functional coverage closure. • Collaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, and other test structures, and review ATPG reports and fault coverage metrics to ensure testability requirements are met. • Support design signoff activities and ensure smooth handoff across implementation stages. • Develop automation and scripting solutions to improve integration, verification, and debug productivity. What we need to see: • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) with 8+ years of experience. • Strong experience in ASIC/SoC RTL Integration. • Excellent understanding of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols. • Strong verification knowledge with hands-on experience in SystemVerilog and UVM. • Ability to independently verify block-level and integration-level designs. • Strong understanding of DFT methodologies including Scan, ATPG, MBIST, LBIST, JTAG, and test compression techniques. • Experience with lint, CDC, RDC, and design quality signoff flows. • Strong debugging, analytical, and problem-solving skills. • Good communication skills and ability to work effectively across multiple engineering teams. Ways to stand out from the crowd: • Experience with large-scale SoC or full-chip integration, including high-speed interfaces, processor subsystems, memory controllers, and third-party IPs. • Exposure to Synopsys, Cadence, or Siemens DFT and verification tools. • Experience with low-power design methodologies and UPF. • Proficiency in Python, Perl, Tcl, or Shell scripting, and a passion for improving engineering productivity through automation and AI-assisted development tools. • Ability to bridge integration, verification, and DFT domains to solve complex system-level challenges and drive efficient design closure. . Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ #LI-Hybrid Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.