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StatisticsPythonMachine learning
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Sponsorship verdict
Sponsorship possible
One solid signal, not two. Worth applying, and worth asking about sponsorship early.
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✓
Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
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The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
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No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
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✓
What Intel Corporation paid sponsored hires in similar roles11 certified filings for “Quality Reliability Engineer” (Industrial Engineers) in AZ: $103k–$130k, median $117k.
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✓
Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Employer is on a government sponsor record
- The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
- No salary bar for this route
- H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles
- 11 certified filings for “Quality Reliability Engineer” (Industrial Engineers) in AZ: $103k–$130k, median $117k. Most were filed at wage level II (50%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.
About the role
Job Details:
Job Description:
About the Team
The Technology Development (TD) Quality and Reliability organization plays a critical role in enabling the successful deployment of next-generation semiconductor technologies through silicon-based quality, reliability, and technology readiness assessments.
The Memory Quality and Reliability team works closely with Design, Device Engineering, Product Development Engineering (PDE), and Yield organizations to develop, characterize, and certify SRAM, Register File (RF), and Fuse technologies for advanced process nodes. The team supports key technology certification and PDK release milestones through memory characterization, silicon data analysis, predictive modeling, and risk assessment.
Role Overview
As a TD Memory Quality and Reliability Intern, you will collaborate with experienced engineers to evaluate advanced memory technologies and help drive technology readiness for future Intel Foundry process nodes. This role offers hands-on experience in memory characterization, silicon data analytics, statistical modeling, and semiconductor technology development.
You will contribute to projects that support technology certification decisions by analyzing silicon data, developing predictive models, and assessing memory performance across various operating conditions.
Responsibilities
Responsibilities may include, but are not limited to:
• Analyze silicon characterization data from SRAM, Register File (RF), and Fuse memory test structures to identify performance trends, variability, and potential risks.
• Support memory characterization activities across voltage, temperature, and process conditions.
• Perform data analysis, visualization, and reporting using Python, JMP, or similar analytical tools.
• Develop and enhance statistical models for Vmin/Vmax prediction and technology readiness assessments.
• Support Silicon-to-Simulation (Sil2Sim) correlation studies and memory characterization methodologies.
• Generate technical reports and contribute to technology certification reviews.
• Collaborate with cross-functional teams including Design, Device Engineering, Process Integration, Product Development Engineering, and Yield Engineering.
• Assist with risk assessment activities and technology certification milestones.
• Present data-driven findings and recommendations to engineering teams and project stakeholders.
Qualifications:
Minimum Qualifications
• Currently pursuing a Ph.D. in Electrical Engineering or a related field.
• Basic knowledge of semiconductor devices, microelectronics, or integrated circuit design.
• Programming or scripting experience using Python or similar languages.
• Experience analyzing technical, scientific, or research data through academic projects, research activities, or previous internships.
• Strong academic performance with a cumulative GPA of 3.0 or higher required.
Preferred Qualifications
Coursework, research, or experience in one or more of the following areas:
• SRAM or memory technologies
• Semiconductor device physics
• VLSI design
• Statistics, machine learning, or data science
• Semiconductor process technology
Experience with:
• Python, Pandas, and NumPy
• JMP or other statistical analysis tools
• Data visualization and statistical modeling techniques
• Large-scale data analysis and predictive modeling
Additional experience in memory architectures, silicon characterization, reliability assessment, or semiconductor test methodologies is highly desirable.
What You Will Learn
During this internship, you will gain exposure to:
• Advanced SRAM, RF, and Fuse memory technologies
• Memory characterization and certification methodologies
• Silicon data analytics and statistical m
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