Jobs / United States / Intel Corporation

Intel Corporation

EDA Tool Software Engineer

4 Locations Posted today

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Skills this job asks for

PythonCustomer serviceJiraGit

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Intel Corporation paid sponsored hires in similar roles139 certified filings for “Software Engineer” (Software Developers) in CA: $144k–$178k, median $156k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Intel Corporation paid sponsored hires in similar roles
139 certified filings for “Software Engineer” (Software Developers) in CA: $144k–$178k, median $156k. Most were filed at wage level III (52%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.   Life at Intel In this role you will be responsible for enabling EDA vendor tools for RC Extraction (StarRC, Quantus, xACT, etc), and EM tools for high-frequency analysis on Intel's process technologies. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. Interaction with EDA vendors is expected for new feature enablement. Intel Foundry Business Group focuses on providing world-class manufacturing capabilities, innovative process technologies, and customized solutions to our global customers. As part of the Intel Foundry organization, you will join a team dedicated to enabling customers' success by bringing their ideas to life through advanced semiconductor solutions. Together, we support Intel's broader mission of creating world-changing technology that improves lives everywhere. Well qualified candidates should possess the following behavioral traits: • Excellent communication and presentation skills for technical and non-technical audiences • High motivation and enthusiasm for self-directed, hands-on work • Creativity and flexibility to thrive under changing priorities and evolving program needs • Strong analytical thinking and problem-solving capabilities • Collaborative mindset with ability to work effectively across diverse teams • Adaptability to work in a fast-paced, innovative environment     You will be working at the intersection of cutting-edge semiconductor technology development and creating solutions that push the boundaries of what's possible in computing. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. Minimum Qualifications: Candidate must possess BS degree with 4+ years of relevant experience, or MS degree with 3+ years of experience or PhD degree in EE/ECE or related field. 2+ years of experience in one of the following two skill sets: Skill set 1: • RC extraction flow enablement such as StarRC or Quantus or SMNS-xACT • Scripting in Perl, or Python or TCL Skill Set 2: • Interconnect Stack development for EDA tools such as ITF, ICT, MIPT, EM stack (Keysight-momentum) or equivalent. • Scripting in Perl, or Python or TCL Preferred Qualifications: 2+ years of experience in the following: • DRC/LVS runset development or validation such as Calibre, Pegasus or ICV. • Customer Support and debugging in RC extraction. • High frequency tools such as Keysight-momentum, Ansys, Cadence-EMX. • Experience with JIRA, GIT. • Proficiency with CMOS process technology. Desired experience: • Electromagnetic (EM) modeling and simulation tools and their application to signal integrity/crosstalk analysis for high-speed/high-density on chip/on package interconnect. • Working with EDA tool vendors to enable customized solutions. Compensation varies depending on number of matching skills, geographical location, and years of experience. Benefits at

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