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Intel Corporation

Staff EMIB-T Substrate Yield Engineer

3 Locations Posted today

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Intel Corporation paid sponsored hires in similar roles287 certified filings for “Process Engineer” (Materials Engineers) in OR: $113k–$133k, median $133k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Intel Corporation paid sponsored hires in similar roles
287 certified filings for “Process Engineer” (Materials Engineers) in OR: $113k–$133k, median $133k. Most were filed at wage level III (87%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

Job Details: Job Description: Intel's APTM organization is seeking a highly driven Staff Technology Development Substrate Yield Lead to drive supplier yield, defect reduction, technical issue closure, and process-control maturity supporting next-generation EMIB-T substrates across Japan suppliers. The team will be chartered to lead yield performance for next-generation advanced packaging technologies, including EMIB-T (Embedded Multi-die Interconnect Bridge with TSV), Intel's most advanced platform for heterogeneous integration partnering with substrate suppliers locally at the HVM factories. This is a high-visibility, high-accountability role with significant responsibility for enabling successful technology development and manufacturing readiness across both Intel Foundry Services (IFS) and Intel Product Groups (IPG).   The ideal candidate is a self-starter who thrives in ambiguous and fast-paced environments, proactively drives issues to closure, and requires minimal supervision. Success in this role requires strong technical depth, urgency in execution, the ability to influence cross-functional teams and suppliers, and a relentless focus on delivering yield and program milestones. This position requires an Expat assignment in Japan.   Key responsibilities • Own day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas. • Lead structured investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment. • Use statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time. • Establish clear supplier actions, owners, completion criteria, control limits, and verification plans. • Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics. • Capture reusable learning and communicate facts, hypotheses, decisions, and residual risks clearly.   Behavioral traits • Strong analytical and problem-solving skills with the ability to make data-driven decisions in complex environments. • Experience working across multiple organizations and influencing stakeholders to achieve results. • Demonstrated ability to independently manage complex technical issues, execute with urgency, and drive actions to closure. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.  This position is not eligible for Intel immigration sponsorship   Minimum Qualifications • Bachelor's degree with +8 years of experience in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline, OR Master's degree with 6+years, OR PhD with 4+years. • 5+ years of experience in: • Semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field. • Hands-on experience in substrate, advanced packaging, or semiconductor yield engineering, including statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution. • Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems.   Preferred Qualifications: • Experience working directly with substrate suppliers and external manufacturing partners. • Demonstrated program leadership experience, including coordinating cross-functional technical teams and driving execution in high-visi

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