Jobs / United States / Intel Corporation

Intel Corporation

Ocotillo Technology Fabrication Yield Device Engineer

US, Arizona, Phoenix Posted today

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Skills this job asks for

StatisticsLeadershipPythonMachine learning

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Intel Corporation paid sponsored hires in similar roles78 certified filings for “Software Engineer” (Software Developers) in AZ: $111k–$140k, median $120k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Intel Corporation paid sponsored hires in similar roles
78 certified filings for “Software Engineer” (Software Developers) in AZ: $111k–$140k, median $120k. Most were filed at wage level II (59%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

Job Details: Job Description: As a Device Integration Engineer, your responsibilities may include but are not limited to: • Driving the factory to produce transistor and discrete electronic devices that perform according to strictly defined specifications. • Collaborating with Module, Integration, and Yield engineers to perform process modifications to produce material that meets quality, reliability, cost, yield, and performance requirements. • Strictly controlling the initial quality metrics at the end-of-line (EOL) in order to screen and disposition material prior to sort and class testing. Extensive analyses are performed in order to determine specific root causes of discrepant device performance. • Continuously improving quality, reliability, cost, and yield using a feedback loop through Integration and Module engineers to address targeting, variability reduction, and containment of poorly performing line segments • Developing solutions to challenging technical problems utilizing a combination of fundamental knowledge of solid-state physics, statistics, and formal problem-solving methodologies. • Independently identifying improvement opportunities and driving implementation • Summarizing complex problems using formal problem-solving strategies and communicating technical reasoning, project timelines, and help needed to senior leaders • Engaging with senior leaders from multiple teams, such as product engineers, assembly test engineers, and technology development engineers to understand and implement process improvement opportunities. The ideal candidate would exhibit the following behavioral traits: • Highly motivated with leadership qualities • Strong interpersonal skills with understanding of how to work with others to accomplish organizational goals • A collaborative and inclusionary mindset • Highly developed written and verbal communication abilities to influence a wide variety of groups at all levels of the organization • Excellent organizational skills with a strong attention to detail • Experience with setting goals and achieving them on schedule • High tolerance of ambiguity in a rapidly changing, fast-paced work environment with the ability to quickly adjust priorities as necessary • Ability to develop creative solutions to challenging problems • Candidate must be able to effectively run meetings at all levels of the organization in order to effectively solve problems as a team and communicate progress to senior leaders Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school/ work/ classes/ research and/or current job role within the semiconductor manufacturing environment. Minimum Requirements:   • Bachelor's of Science in Electrical Engineering, Physics, Material Science, or related STEM field AND 2+ years relevant experience in the semiconductor industry. • Master’s  of Science in Electrical Engineering, Physics, Material Science, or related STEM field Preferred Qualifications: • A comprehensive understanding of device physics, semiconductor processing, familiarity with failure analysis techniques, basic coding/scripting ability in JSL/SAS/Python, experience in data extraction, statistical process control, statistical data analysis and interpretation, familiarity with statistical software packages such as JMP or Minitab, and familiarity with DOE techniques • Familiarity with latest machine learning tools applied to process and device analysis to accelerate root cause determination • Experience in semiconductor process integ

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