Jobs / United States / Nvidia Corporation
Senior System Integration and Validation Engineer
Nvidia Corporation · 🇺🇸 US, CA, Santa Clara
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 394 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Nvidia Corporation paid sponsored hires in similar roles701 certified filings for “Engineer Senior Systems Software” (Software Developers) in CA: $173k–$214k, median $190k. Most were filed at wage level IV (82%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Nvidia Corporation
The US Department of Labor certified 2,374 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 394 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Nvidia Corporation →
About the role
The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs. Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping! The two hardest, highest-leverage problems in this seat: • Find critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence. • Build AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions. What you’ll be doing: • Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing. • Lead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes. • Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage. • Design and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate. • Translate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving. • Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs. • Lead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs. What we need to see: • BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), plus 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products. • Hands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior — with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive. • At least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned. • Demonstrated AI-driven validation workflow you built or scaled, not just used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or esc