Jobs / United States / Intel Corporation
Senior Standard Cell Library Engineer
Intel Corporation · 🇺🇸 2 Locations
Sponsorship verdict
Sponsorship possible
One solid signal, not two — worth applying, and worth asking about sponsorship early.
- Employer is on a government sponsor recordThe US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
- The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
- No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Intel Corporation paid sponsored hires in similar roles287 certified filings for “Process Engineer” (Materials Engineers) in OR: $113k–$133k, median $133k. Most were filed at wage level III (87%) — 3 lottery entries, ≈46% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
- Confirmed live todayWhen a source last listed this job as open.
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence; it is not legal advice and never a guarantee — the employer and the immigration authority decide. Sign in to factor in where you can already work.
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Sponsor Radar — Intel Corporation
The US Department of Labor certified 1,731 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. USCIS also records 1,112 H-1B approvals in FY2023. Source: LCA disclosure data (US Department of Labor (OFLC)).
Past sponsorship or register membership never guarantees sponsorship for this vacancy or for you. Full Sponsor Radar for Intel Corporation →
About the role
Job Details: Job Description: About the Organization Intel's Foundry Standard Cell team is seeking a talented and motivated Senior Design Engineer to join our growing team . In this role, you will design leading edge experiments to develop, characterize , and test standard cells . You will play a critical role in enabling customer s by listening to their needs and building the solutions . Key Responsibilities • Defines, implements, characterizes, and validates design solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost. • Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability to achieve goals. • Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies. • Reviews and validate s work to ensur e compliance with design, manufacturing, and quality requirements. • Fast turn-around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders). • Run end - to - end flows to generate, validate , and release custom standard cell collateral per on demand requests . Core Competencies • Strong written and verbal communication skills are required with the ability to tailor the communication based on the audience . Qualifications: The Minimum qualifications lis ted below are required to be initially considered for this position . Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: • Bachelor's degree in : Electrical Engineering , Ele ctroni cs Engin eering, N anos cience , M ic r o elec tro nics, Computer Engineering , or a STEM related field . • 2+ years' experience in one or more of the following: • Standard cell layout • Standard cell abstract modeling • Standard cell characterization • ASIC design and verification • Experience using one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre. Preferred Qualifications: • Post Graduate Degree in : Electrical Engineering , Ele ctroni cs Engin eering, N anos cience , M ic r o elec tro nics, Computer Engineering , or a STEM related field . • Unix proficiency and basic software skills using command line languages ( csh , bash, perl , python) are highly valued. We are looking for innovative thinkers ready to make an impact in the evolving semiconductor landscape. Apply today and be part of Intel's mission to create technologies that connect and enrich lives globally. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, California, Folsom Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexua