Jobs / United States / Renesas Electronics America INC

Renesas Electronics America INC

Staff Analog Design Engineer

Chandler, Arizona, US Posted 18 days ago

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Sponsorship verdict

Sponsorship possible

One solid signal, not two. Worth applying, and worth asking about sponsorship early.

  • Employer is on a government sponsor recordThe US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Renesas Electronics America INC paid sponsored hires in similar roles4 certified filings for “Staff Analog Engineer” (Electronics Engineers, Except Computer) in GA: $137k–$199k, median $161k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
Employer is on a government sponsor record
The US Department of Labor certified 56 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Renesas Electronics America INC paid sponsored hires in similar roles
4 certified filings for “Staff Analog Engineer” (Electronics Engineers, Except Computer) in GA: $137k–$199k, median $161k. Most were filed at wage level IV (67%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.

About the role

Renesas is seeking a Staff Analog Design Engineer to serve as a technical focal point for major analog and power-management circuit blocks within complex PMIC and mixed-signal products. In this role as a Staff Analog Design Engineer, you will apply specialized technical expertise to challenging circuit-design problems, determine appropriate methods and technical approaches for new assignments, and own significant designs from architecture and feasibility through silicon validation and production. You will remain hands-on in circuit design while providing technical guidance, leading design reviews, mentoring other engineers, and improving analog-design methods, reusable IP, and engineering practices. Relocation assistance is available for qualified candidates throughout the United States. Responsibilities • Serve as the technical owner for major analog and power-management circuit blocks. • Translate product requirements into block- and subsystem-level architectures and design strategies. • Lead the design, simulation, verification, and layout supervision of complex CMOS power-management circuits. • Determine design methods, techniques, and evaluation criteria for complex new assignments. • Conduct feasibility studies and architectural trade-off analyses for new circuit concepts. • Own circuit performance against functional, power, area, robustness, quality, and schedule requirements. • Lead technical and design reviews for assigned circuitry and provide technical guidance to other engineers. • Work closely with Layout Engineering to optimize physical implementation and resolve layout-dependent performance issues. • Lead laboratory evaluation and silicon characterization activities in collaboration with Applications and Validation Engineering. • Identify and resolve complex cross-functional design issues during silicon bring-up and production ramp. • Collaborate with DFT, Verification, Test, and Product Engineering on chip-level verification, test strategy, qualification, and production readiness. • Develop and improve analog-design methods, reusable IP, technical practices, and design documentation. • Coach and mentor less experienced analog designers and serve as a technical resource within the engineering team. • Support customer-facing technical discussions and RFQ activities as part of the broader project team. • Demonstrated depth of experience in analog or mixed-signal integrated circuit design. • Strong CMOS transistor-level design, simulation, verification, and debugging capability. • Experience designing complex analog and/or power-management circuits. • Experience taking significant circuit blocks from specification through tape-out, silicon evaluation, and production. • Strong understanding of analog layout considerations, parasitics, matching, noise, stability, and physical-design trade-offs. • Ability to independently select and adapt design methods, techniques, and evaluation criteria for complex engineering problems. • Demonstrated ability to conduct design reviews and provide effective technical guidance. • Experience collaborating across Analog, Digital, Verification, Layout, Applications, Test, and Product Engineering. • Strong analytical, problem-solving, written, verbal, and presentation skills. • Ability to work independently while collaborating effectively across global engineering teams. Preferred Qualifications • Experience with PMICs, DC/DC converters, LDOs, charger products, control loops, voltage and current references, or other power-management technologies. • Experience with mixed-signal or top-level verification. • Experience with silicon characterization, laboratory evaluation, and root-cause analysis. • Experience developing reusable analog IP or improving circuit-design

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