Senior Director, Hardware Engineering

The Senior Director, Central Engineering will lead the development of advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines. This role is responsible for establishing scalable design and verification methodologies, driving SystemC and SystemVerilog model development, and leveraging AI-driven techniques to improve productivity, quality, and time-to-market for complex semiconductor SoCs.   The ideal candidate is a recognized technical leader with deep expertise in SoC architecture, system modeling, RTL development, and engineering process transformation. They will partner with product groups, platform teams, and executive leadership to define and deploy next-generation design methodologies that accelerate innovation and enable reuse across the organization. Key Responsibilities Technical Leadership • Define and drive the strategic roadmap for SoC design methodologies across the company. • Lead architecture reviews and technical direction for complex SoC and subsystem developments. • Establish best practices for hardware/software co-design and model-based development. • Provide technical leadership for cross-functional teams spanning architecture, design, verification, emulation, and software. System Modeling & Virtual Platforms • Lead development of transaction-level and architectural models using SystemC/TLM . • Define methodologies for building executable SoC specifications and virtual platforms. • Drive alignment between SystemC models, RTL implementations, and software development environments. • Enable early software development and system validation using virtual prototypes. Design & Verification Methodology • Develop and standardize SoC modeling and verification flows using SystemVerilog , UVM, and related methodologies. • Promote reusable IP, subsystem, and SoC-level modeling frameworks. • Drive methodology adoption across product groups to improve predictability, quality, and reuse. • Establish metrics and KPIs to measure design productivity and model accuracy. AI-Driven Engineering Innovation • Define and implement AI-enabled methodologies for model generation, verification, and validation. • Evaluate and deploy Generative AI, LLMs, and automation technologies to improve engineering efficiency. • Create workflows that leverage AI for: • SystemC model generation • SystemVerilog model development • Verification content generation • Coverage analysis • Design documentation • Requirement traceability • Lead pilot programs and organization-wide adoption of AI-assisted design methodologies. Organizational Leadership • Build and lead high-performing engineering teams. • Mentor directors, principal engineers, and distinguished engineers. • Foster collaboration across Central Engineering, Product Groups, and external partners. • Influence long-term semiconductor technology and platform strategy. Education • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. • Master's degree or Ph.D. preferred. Experience • 15+ years of experience in semiconductor or SoC development. • 8+ years of technical leadership experience managing large engineering organizations and complex programs. • Proven experience leading SoC architecture, design, or verification teams. Technical Skills • Strong understanding of: • SoC architecture and integration • Digital design methodologies • IP and subsystem development • Hardware/software co-design • SoC verification methodologies • Hands-on experience with: • SystemC/TLM model development • SystemVerilog and UVM-based verification environments • Virtual platforms and executable specifications • SoC performance modeling • Design and verific