Sponsorship verdict
Sponsorship possible
One solid signal, not two. Worth applying, and worth asking about sponsorship early.
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✓
Employer is on a government sponsor recordThe US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first.
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The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
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No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
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✓
What Hewlett Packard Enterprise Company paid sponsored hires in similar roles5 certified filings for “VLSI Engineer III” (Electronics Engineers, Except Computer) in CA: $157k–$186k, median $186k.
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Confirmed live todayWhen a source last listed this job as open.
Details and sources
- Employer is on a government sponsor record
- The US Department of Labor certified 486 H-1B/E-3 labor condition applications for this employer between Oct 2025 and Jun 2026 (latest Jun 2026) — the step every H-1B hire needs first. Source: LCA disclosure data (US Department of Labor (OFLC)).
- No salary bar for this route
- H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
- What Hewlett Packard Enterprise Company paid sponsored hires in similar roles
- 5 certified filings for “VLSI Engineer III” (Electronics Engineers, Except Computer) in CA: $157k–$186k, median $186k. Most were filed at wage level II (50%) — 2 lottery entries, ≈31% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).
US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).
A verdict summarises public evidence. It is not legal advice and never a guarantee: the employer and the immigration authority decide. Sign in to factor in where you can already work.
About the role
Principle VLSI/ ASIC Design Engineer
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
The Principle VLSI/ASIC Design Engineer is responsible for the architecture, RTL design, implementation, and analysis of complex VLSI components and system-on-chip (SoC) solutions. This role contributes to early-stage architecture and design exploration and carries concepts through detailed design implementation for networking, compute, and other complex SoC applications.
The engineer will serve as a recognized technical authority in ASIC and VLSI design, influencing product strategy, technology roadmaps, architectural direction, and implementation methodologies across organizations and business units. The role requires strong technical leadership, innovation, cross-functional collaboration, and the ability to mentor engineers while delivering high-quality, scalable, and production-ready designs.
Key Responsibilities
• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectural approaches, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
• Design, develop, and modify complex RTL blocks using industry-standard hardware description languages and design practices.
• Drive RTL implementation from architectural definition through synthesis, physical implementation support, timing closure, and production readiness.
• Analyze design tradeoffs involving performance, power, area, scalability, reliability, and time to market.
• Develop and evaluate VLSI components and hardware systems across multiple platforms and product organizations.
• Conduct design reviews and evaluate product designs for compliance with architecture, implementation guidelines, quality standards, and industry best practices.
• Establish operating data and performance expectations through analytical modeling, simulation, prototyping, and experimental evaluation.
• Provide tangible, data-driven feedback to improve product quality, reduce design risk, and mitigate potential product failures.
• Contribute to organization-wide ASIC design architectures, methodologies, and standards.
• Create integration plans for incorporating new technologies, IP, design practices, and implementation improvements into existing architectures.
• Identify emerging technologies, innovations, tools, and external partnerships that support business objectives and technology roadmaps.
• Review material specifications, hardware designs, electrical component requirements, and related technical documentation.
• Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, and external development teams.
• Influence technical decisions made by business leadership, development partners, suppliers, and industry standards organizations.
• Provide technical leadership for significant projects and programs, conne
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