Jobs / United States / Graphcore Limited

Graphcore Limited

Principal Debug Validation Engineer

Austin, Texas, United States Posted today

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Skills this job asks for

C++PythonMachine learningLinuxCommunicationStatistics

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Sponsorship verdict

No sponsorship evidence yet

No government record and no wording either way. Not a refusal: ask the recruiter.

  • No government sponsor record hereThis employer does not appear with approvals in the government data SponsorApply holds.
  • The posting doesn’t mention sponsorshipSilence isn’t a refusal — ask the recruiter before investing much time.
  • No salary bar for this routeH-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area.
  • What Graphcore Limited paid sponsored hires in similar roles2 certified filings for “Rack and Blade Level Validation Director” (Computer and Information Systems Managers) in TX: $242k–$383k, median $312k.
  • Confirmed live todayWhen a source last listed this job as open.
Details and sources
No salary bar for this route
H-1B has no fixed salary bar: the employer must pay at least the prevailing wage for the role and area. Cap-subject employers enter a lottery weighted by wage level. Source: https://www.federalregister.gov/documents/2025/12/29/2025-23853/weighted-selection-process-for-registrants-and-petitioners-seeking-to-file-cap-subject-h-1b, rules effective 2026-02-27.
What Graphcore Limited paid sponsored hires in similar roles
2 certified filings for “Rack and Blade Level Validation Director” (Computer and Information Systems Managers) in TX: $242k–$383k, median $312k. Most were filed at wage level IV (100%) — 4 lottery entries, ≈61% projected selection odds for cap-subject employers. Source: US Department of Labor LCA disclosure data (Oct 2025 – Jun 2026).

US H-1B: cap-subject employers enter a lottery weighted by wage level — Level I gets 1 entry, Level IV gets 4 (DHS projected selection odds ≈15% at Level I to ≈61% at Level IV). Universities and non-profit research employers are cap-exempt. The $100,000 fee for new petitions from abroad is currently blocked by a court order (appeal pending).

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Before you apply

Sponsorship unknown

No register record and no sponsorship wording in the posting. Worth asking the employer before investing significant time.

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About the role

Principal Embedded SW/FW Engineer (Bringup) - Austin, Tx, USA Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms. You will play a key role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties • Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon • Deploy silicon validation tests on first silicon and debugging them • Develop automated test framework and regression test suites in Python to optimize validation efficiency • Collaborate closely with engineers from many other disciplines on a variety of topics • Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies • Analyse test results, identify and debug failures/defects • Contribute to shared test and validation infrastructure • Provide feedback to architects Candidate Profile Essential: • Understanding of ML applications and their workloads • A self-starter who can apply independent judgement • A team player able to lead and support colleagues with difficult concepts • Strong experience in Bare metal / embedded C/C++ • Excellent problem-solving, analytical & diagnostic skills • Ability to work across teams and programming languages to find root causes of critical and complex issues • Experience of the post-silicon validation process applied in digital ASIC environments • Python, Linux • Excellent communication skills and the ability to explain difficult concepts to resolve issues Desirable • 5 to 10 years’ experience • Experience building and leading, multi-site teams • Driver level experience with one or more of the following is highly desirable: • PCIe • Ethernet • Memory technologies (LPDDR, DDR, HBM, …) • Other peripherals such as I2C, I3C, SPI, … • Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable. • Experience of Arm CPUs, System IP and debug tools. • Experience of AMBA protocols. • Experience in Characterization, Failure Analysis, Test Development, Statistical analysis,

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